Chip lifecycle / Work products / Test chip RTL

Test chip RTL

The register transfer level source of the test chip, including the blocks under evaluation, integrated IP and test and debug structures.

Source Work product in the Fabless startup chip lifecycle

Why it exists and what it decides

The test chip RTL embodies the ideas the company is trying to prove in silicon, and it also feeds the software prototype platform. It must be verified and frozen in time for the shuttle. Without a controlled release, physical design and software use different versions and the test chip may not show what it was meant to.

Decisions it informs

Whether the RTL is complete and verified enough for the test chip tape-out
Which debug and observation features to include
Which late fixes are allowed before the shuttle deadline

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