A model that predicts the correct behaviour of the design, used by verification to check results.
Model Work product in the SoC and full-chip lifecycle
It predicts the correct output for any input, so verification can check the design automatically rather than by inspection. Without an independent reference, checkers repeat the designer's assumptions and functional bugs pass undetected.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.