The design of spare rows and columns in the memory array and the method for finding failing cells and replacing them with spares during test.
Specification Work product in the Memory product lifecycle (DRAM, NAND and HBM)
Large memory arrays always contain some failing cells, and without repair the yield of large dies would be uneconomic. The scheme balances repair capability against die area and test time. Without a well designed scheme, yield falls during ramp, or area is wasted on spares that are never used.
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