The agreed plan for the product: features, target cost, schedule and the main risks, shared by business and engineering.
Plan Work product in the SoC and full-chip lifecycle, the AI accelerator lifecycle, the Memory product lifecycle (DRAM, NAND and HBM), the Silicon photonics and optical interconnect lifecycle, the RF and mmWave product lifecycle, the System development lifecycle, the FPGA chip development lifecycle and the Product lifecycle
It is the agreement between business and engineering on what will be built, for what cost, by when and with which resources. Without it, scope grows unchecked, cost and schedule targets are implicit and teams cannot tell which trade-offs the business will accept.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.