Test chip dies assembled into packages and ready for bring-up, characterisation and evaluation.
Physical item Work product in the Hard IP lifecycle and the Fabless startup chip lifecycle
The test chip can only be evaluated once dies are packaged and mounted on boards, and the packaged parts are the physical evidence that the design works. Tracking them keeps every result tied to a lot. Without enough properly packaged and traced parts, characterisation is delayed and results cannot be linked to wafers or assembly lots.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.