The design of the package the die sits in: substrate, connections, thermal path and pin-out.
Design data Work product in the SoC and full-chip lifecycle, the AI accelerator lifecycle, the Fabless startup chip lifecycle, the Memory product lifecycle (DRAM, NAND and HBM), the Silicon photonics and optical interconnect lifecycle and the MEMS and sensors lifecycle
It defines how the die connects to the board and how heat leaves it, which shapes pin-out, signal integrity, power delivery and cost. Early co-design with the die keeps bump plans from clashing, lets power and signal integrity close and avoids a package redesign after tape-out.
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