The detailed design description of the accelerator blocks: compute array organisation, pipelines, buffers, control logic and interfaces, written before and alongside the RTL.
Specification Work product in the AI accelerator lifecycle
It explains how each block realises the architecture, so RTL designers implement a reviewed design and verification and performance teams know what to check and model. Decisions that live only in code let the performance model diverge from the design and stop reviews catching structural mistakes before RTL freeze.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.