Simplified physical views of an IP block that show its size, pins and blocked areas, so the SoC can place and route around it.
Design data Work product in the SoC and full-chip lifecycle and the Soft IP lifecycle
They let the SoC place and route around an IP block using only its outline, pins and blockages, without the full layout. If an abstract does not match the real layout, the SoC routes over blocked areas or misses pins, and the errors appear only in full-chip physical verification.
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