A running log of process integration problems found on test chips and full-flow wafers, each with its symptoms, suspected cause, owner, actions and status.
Record or register Work product in the Process technology (node) lifecycle and the System development lifecycle
It keeps integration problems visible until they are solved, so yield readiness reflects real progress. Rediscovered issues and ownerless stalled actions leave the yield readiness review blind to what is still open.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.