The planned arrangement of the macro: its outline, the placement of its blocks, the location and layer of each pin, the power grid, the blockages and the keep-out areas the integrator must respect.
Design data Work product in the Hard IP lifecycle
Integrators floorplan their chips around the macro long before it is finished, so its outline and pins must be stable early. The floorplan is also the start of the layout and of the test chip plan.
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