The joint plan of the accelerator die floorplan and its package: compute and memory placement, high-bandwidth memory or chiplet placement, bump plan, power delivery and thermal path.
Design data Work product in the AI accelerator lifecycle
Large accelerators are limited by die size, memory bandwidth, power delivery and heat, all of which depend on how die and package are planned together. Planned apart, memory interfaces cannot be placed, power cannot be delivered and package and board work starts from wrong assumptions.
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