The specification of the programmable fabric: the logic block, routing architecture, block memories, arithmetic blocks, clock network and input and output structure, with the targets they were chosen to meet.
Architecture Work product in the FPGA chip development lifecycle
Every tile, the device model in the software and the test strategy are built from this specification, and it cannot change after tape-out. Freezing it on recorded benchmark evidence protects the family from late changes that ripple through tiles and software.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.