The netlist of the macro taken from the final layout, with the resistance and capacitance of the wires and devices, used for verification after layout, characterisation and test pattern work.
Design data Work product in the Hard IP lifecycle
The views and the verification after layout are only as good as the netlist they use. Recording the layout and kit versions ties every result back to the layout that will be released.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.