The specification of the design-for-test features in a chip: scan architecture and compression, memory built-in self-test, boundary scan, test access ports, analog test access and test modes.
Architecture Work product in the Test program and ATE development lifecycle
It decides how testable the chip will be and how much test will cost. Without an agreed architecture, test access is added late, coverage targets are missed and test time is far higher than needed.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.