The arrangement of the device: where the fabric columns, hard IP blocks, configuration logic, clock and power networks and the input and output ring sit, for each family member.
Design data Work product in the FPGA chip development lifecycle
The floorplan decides how hard IP connects to the fabric and how the design software sees the device. Agreeing it early lets tile design, hard IP integration and physical design work from the same picture.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.