The plan for which customers receive engineering samples, how many, when, and with what support.
Plan Work product in the SoC and full-chip lifecycle, the Memory product lifecycle (DRAM, NAND and HBM), the Silicon photonics and optical interconnect lifecycle and the Product lifecycle
It decides which customers get scarce early parts, when and with what support, so samples create design wins rather than confusion. Samples that go to the loudest requester share no known issues and collect no feedback.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.