The measure of how thoroughly the design has been exercised by verification, against the goals in the verification plan.
Report Work product in the SoC and full-chip lifecycle, the AI accelerator lifecycle and the FPGA chip development lifecycle
It measures how much of the design and its intended behaviour verification has exercised, so sign-off rests on evidence rather than test counts. Untested features, unreached states and dead code can otherwise reach tape-out unnoticed.
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