Scan, memory test and functional patterns translated from simulation formats into the selected tester's format, with timing, levels and pin mapping applied, ready to load into the test program.
Test Work product in the Test program and ATE development lifecycle
It is the bridge between simulation and the tester, and errors here make good patterns fail on good silicon. Without careful conversion, timing or pin mapping errors waste first silicon time on debugging the patterns rather than the chip.
The full lifecycle detail, with its charts, flows, tables and every section, is for registered members. Registration is free and takes a minute. You come back to this page afterwards.