The design of the interface between a stacked memory's base die and its host, and between the base die and the memory dies above it: physical layer, signal assignment, timing and test access.
Design data Work product in the Memory product lifecycle (DRAM, NAND and HBM)
In high bandwidth memory the base die links a wide host interface to the stacked dies, so its design determines bandwidth, power and testability of the whole stack. It must be frozen before the stack design can be fixed. Without it, stack configuration, bump maps and the package cannot be finalised and interoperability with host processors is at risk.
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