Scan test patterns produced by automatic test pattern generation to detect manufacturing defects in digital logic using fault models such as stuck-at, transition delay and cell-aware faults.
Test Work product in the Test program and ATE development lifecycle
It is the main screen for defects in digital logic and a large share of test time. Without good patterns, defective parts escape to customers, or redundant patterns waste tester time; patterns that fail on good silicon stall the first silicon schedule.
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