Chip lifecycle / Work products / Array and periphery architecture

Array and periphery architecture

The architecture of the memory die: how the cell array is divided into banks, sub-arrays and mats, and how sense amplifiers, decoders, control logic and data paths are arranged around it.

Architecture Work product in the Memory product lifecycle (DRAM, NAND and HBM)

Why it exists and what it decides

In memory, die size and therefore bit cost depend heavily on how efficiently the array and periphery are arranged. The architecture fixes this early, using the chosen cell and array concept. Without it, circuit and layout teams make local choices that waste area, miss speed targets or complicate redundancy and test.

Decisions it informs

How the array is partitioned into banks and sub-arrays
Where periphery blocks sit and how much area they take
Whether the architecture supports the product plan's density, speed and power targets

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