A study comparing candidate accelerator architectures, such as compute array organisation, memory system and interconnect, against the target workloads and constraints.
Analysis Work product in the AI accelerator lifecycle and the FPGA chip development lifecycle
It lets the team choose the architecture on evidence from the target workloads rather than preference, while the cost of changing direction is low. Skip it and the design may commit to an organisation that is compute bound where workloads are memory bound, an error that appears only on silicon.
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