Chip lifecycle / Work products / Architecture model

Architecture model

An executable model of the proposed chip architecture, used to compare options and check that performance goals can be met before design starts.

Model Work product in the SoC and full-chip lifecycle and the Fabless startup chip lifecycle

Why it exists and what it decides

It lets the architecture team test candidate organisations of the chip against target workloads before any RTL exists, when changes are still cheap. A specification frozen on judgement alone finds performance shortfalls in emulation or silicon, when the fix costs a respin or a missed market window.

Decisions it informs

Which architecture option goes forward into the architecture specification
Whether the performance and power targets are achievable with the chosen interconnect and memory system
Where the design needs more bandwidth, buffering or compute before specification freeze

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