1. Purpose of the gate
DFT alignment is the point where the chip's design team and the test team agree the test features the chip carries and how each will be used on the tester. After it, the design team builds to the agreed DFT architecture, and changes go through the chip's change control.
It matters because test time, coverage limits and the way the tester reaches each block are fixed by the DFT architecture. A feature that is missing or awkward to reach costs test time on every part shipped.
The design team and the test team agree the test features the chip carries and how each one will be used on the tester, so the design can be built to be testable at the cost the plan allows.
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