1. Purpose and scope
The test chip is the company's first silicon and the first time its claims meet real manufacturing. Its purpose is not to be a product: it is to produce measured evidence on the risks that a prototype cannot settle, such as clock rate, power, analog behaviour, memory performance and the interaction of the company's design with the selected node. The same design and verification disciplines as a full chip apply, on a scope chosen to prove the riskiest parts.
A shuttle has a fixed cut-off date, and missing it usually means waiting for the next run, which can cost a significant part of the company's runway. The schedule is therefore built backwards from the cut-off, through sign-off, to the RTL freeze that closes this stage. This stage owns the design and its stability: when it ends, the RTL is complete for the scope, the licensed IP is in, most of the verification plan has run and the implementation flow has shown no blocking timing or area problem, so that sign-off can close on a design that no longer moves.
In scope: test chip RTL, IP integration, verification on the reduced scope up to the RTL freeze, DFT and debug features, implementation trials on each RTL drop, running the RTL on the prototype platform as it matures, the packaging decision and the first drafts of the pad ring, test board, package plan and evaluation plan. Out of scope: closing verification and physical sign-off on the frozen RTL, which belong to Test Chip Sign-off, and releasing the database and measuring returned silicon, which belong to Test Chip Tape-out, Bring-up & Evaluation.
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