1. Purpose and scope
This is the full chip design flow, usually for the company's first full mask set. Unlike the test chip, which proved the riskiest parts on a shared shuttle, product silicon carries every function the first customer needs, on the production node, in the production package, with production test. A respin costs a new mask set and months of schedule that a startup's runway may not cover, so the work is organised around getting first silicon right. Licensed IP and a design services partner usually carry more of the work than in an established team, which makes clear interfaces, deliverable checks and shared criteria essential.
This stage owns the design. It ends when the product RTL is feature complete against the frozen specification, the licensed IP is integrated at recorded versions, the test chip blocks carry their fixes and the verification plan has been extended to the full product scope with most of it run, so that verification, test and physical sign-off can close on a design that no longer moves.
In scope: product RTL with integrated IP, verification up to the RTL freeze, power intent verification, the DFT architecture and its insertion, implementation trials on each RTL drop on the production node, floorplan and package co-design, the developing test strategy and the start of firmware on the prototype platform. Out of scope: coverage closure, test pattern generation and physical sign-off on the frozen RTL, which belong to Product Silicon Sign-off; the release of the database, the mask order and work on silicon, which belong to Product Silicon Tape-out, Bring-up & Sampling.
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