1. Purpose and scope
RTL design produces the register-transfer level description of the whole chip. In a SoC most of the logic arrives as IP, so the chip team's own code is the top level, the interconnect configuration, the glue between blocks, the chip-specific blocks that differentiate the product, and the chip-level infrastructure for clocks, resets, power management, debug and security.
The stage ends at RTL freeze, when the code is feature complete and only reviewed bug fixes are accepted. That boundary matters because verification, DFT, physical design and software all plan their closure from it. A freeze that is declared before the features are really complete pushes risk into every later stage.
Scope includes the quality of the code as well as its function: lint, clock and reset domain crossing checks, power intent, synthesizability, and early evidence from trial synthesis that the design can meet area, timing and power budgets.
12 more sections for registered members.