Physical Design & Sign-off: stage guide (SoC and full-chip lifecycle)

Physical Design & Sign-off: stage guide

How the full-chip netlist, with each IP block's physical views, becomes a manufacturable layout that meets timing, power and physical rules. It covers floorplanning, synthesis, placement, clock tree, routing, static timing analysis, power integrity, physical verification, engineering change orders and boot code freeze, up to physical sign-off. It is written for physical design and timing engineers, and for the design, DFT, packaging and foundry teams who feed the layout.

1. Purpose and scope

Physical design turns logic into geometry. The layout must fit the die, meet timing at every corner and mode the product will see, deliver clean power to every cell, survive electromigration over the product's life, and obey every design rule of the foundry's process. Physical sign-off is the evidence that all of this is true on the final layout, and that the layout matches the netlist it came from.

Work starts long before the stage formally begins: die size estimates during specification, floorplanning during RTL design and trial layouts during verification. The stage proper begins once the netlist is stable and the process design kit is at a version the team accepts for sign-off, and ends at physical sign-off.

Scope includes chip-level concerns that cut across blocks: the floorplan and power grid, the placement of hard IP and memories, the clock network, the input and output ring and its fit with the package, and the integration of each block's abstract views and timing models.

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