1. Purpose of the gate
Qualification shows that the chip, made the way it will be made in production, will survive the stresses of its intended use for its intended life. Results only count if the parts tested represent production. This gate makes sure they do: the parts were built on the intended fab process, package, assembly site, test program and screening flow, from the silicon revision that will ship, and the qualification plan that will test them is approved.
Two criteria apply. The parts must be built on the production flow, with any difference declared and judged acceptable. The qualification plan must be approved, naming the standard being qualified to, such as JEDEC JESD47 for general use or AEC-Q100 for automotive, the stress tests, the sample sizes the standard requires, the lots, the pass criteria and the schedule.
This gate is where the risk of samples that do not match production is confronted directly. Parts built on an engineering flow, with a different package supplier or an unreleased test program, can pass qualification and still fail in production. The gate also prepares for qualification failures, by making sure failure analysis capacity and a plan for a failed stress are in place before testing starts.
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