1. Purpose of the gate
Tape-out is the point from which a design fix costs new masks. Before it, a problem found in the design is corrected in the database; after it, the same problem means a new mask set, new wafers and a later sample date. The business tracks tape-out as a gate of its own for that reason, and because it starts the first silicon build: the mask and first wafer order is placed, the foundry's clock starts and every date that follows, from first silicon to customer samples, is counted from here.
The product lifecycle sets four criteria. Design sign-off is complete, with waivers reviewed and approved. The foundry hand-off package is accepted by the foundry. The mask and first wafer order is placed. And the bring-up and validation plans are ready for the first parts. The first two belong to engineering, the third to supply chain and operations, and the fourth to engineering with validation and field applications. The gate brings them together because a tape-out with a perfect database and no plan for the parts that come back wastes the time it bought.
The gate sits near the end of Development, in the Development status of the product, just before design release closes it. Tape-out concerns the chip or each die; design release then confirms that the product as a whole is ready to build, including packages, boards, agreements and the sampling plan. For a multi-die product, the chiplet lifecycle's multi-die tape-out feeds design release, while the tape-out of each die is tracked here.
The waivers accepted at this gate matter well beyond engineering. Every waiver becomes an erratum, a workaround or a planned revision that the business has to schedule, price and tell customers about, so the product line manager and the quality engineer review them alongside engineering.
| Engineering gate | Lifecycle | Relation | What it brings to this gate |
|---|---|---|---|
| Tape-out | SoC | Matches | The GDSII database and the foundry hand-off package for the chip. |
| Tape-out or SoC hand-off | Analog and mixed-signal | Matches | The tape-out database of a stand-alone circuit, or its hand-off to the SoC. |
| Tape-out | Automotive | Matches | The layout database signed off for the mission profile and temperature grade. |
| Tape-out | AI accelerator | Matches | The tape-out database and the package design released to manufacture. |
| Tape-out | Memory | Matches | The die database released to mask making, with the mask order. |
| Tape-out | Space | Matches | The tape-out database signed off with the radiation rules and export classification confirmed. |
| Tape-out | Photonics | Matches | The photonic tape-out database with the test structures wafer-level optical test needs. |
| Interface ASIC tape-out | MEMS | Matches | The interface chip's tape-out database, with its trim architecture fixed. |
| Tape-out | RF | Matches | The radio chip's tape-out database and hand-off package. |
| Chip tape-out and board design release | Medical | Matches | The medical chip's tape-out database, released under design control. |
| Tape-out | FPGA device | Matches | The first family member's release to manufacture, with its tile timing views. |
| Custom layer tape-out | Structured ASIC | Matches | The custom layer tape-out database, with banked base wafers allocated. |
10 more sections for registered members.