1. Purpose of the gate
Design release is the point at which the product stops being a design and starts being built. It is the product-level roll-up of the release gates the engineering lifecycles hold themselves: the SoC lifecycle's tape-out, the IP lifecycle's release of each block, the analog and mixed-signal tape-out or SoC hand-off, the chiplet lifecycle's die and package supply agreement and its multi-die sign-off and tape-out, and the FPGA lifecycle's board release and timing-clean bitstream. Each of those gates decides whether one part is ready. Design release decides whether the product as a whole is ready to commit manufacturing spend.
That distinction is why the gate exists separately. A chip can be ready for tape-out while the product is not: the substrate supplier may not be contracted, a software licence may be unsigned, or nobody may have planned how first parts will be validated and sampled. The product lifecycle sets five criteria here: engineering sign-offs complete for every engineering lifecycle in the product, waivers reviewed and approved, suppliers ready to build, licence and partner agreements signed for everything the product uses, and validation and sampling plans drafted.
Design release is expensive to reverse. Masks, wafers, substrates and boards are paid for once the release goes out, so the gate concentrates on whether open items are understood and accepted rather than on re-running engineering reviews that each lifecycle has already held.
| Engineering gate | Lifecycle | Relation | What it brings to this gate |
|---|---|---|---|
| Tape-out | SoC | Feeds | The GDSII database and foundry hand-off package: the chip's release for manufacture and the main input here. |
| IP release | IP | Feeds | The IP release package and integration guide for every block, released and integrated before the product releases. |
| Tape-out or SoC hand-off | Analog and mixed-signal | Feeds | The tape-out database or the integration views handed to the SoC. |
| Die and package supply agreed | Chiplet | Feeds | Supplier agreements and the cost model for dies, substrate and assembly. |
| Multi-die tape-out | Chiplet | Feeds | Die tape-out databases and interposer and substrate manufacturing data, released together. |
| Board released for build | FPGA | Feeds | Board layout and fabrication data. |
| Timing closure and bitstream | FPGA | Feeds | A timing-clean bitstream and its timing report. |
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