1. Purpose and scope
Test vehicles play the part that first silicon plays for a chip, with a different aim: they are measured to learn about the process, not to validate one design. A typical test vehicle combines SRAM arrays, which are dense and sensitive enough to reveal random defects and marginal devices, defect monitors such as comb, serpentine and via chain structures that localise shorts and opens by layer, ring oscillators that show speed and its spread, device arrays for parametric data, and early reliability structures. Scribe line structures on every wafer add a steady stream of parametric data.
The purpose of this stage is yield learning: finding the mechanisms that kill or degrade circuits, ranking them in a defect Pareto, assigning owners and driving them down, so that defect density and parametric spread follow the planned learning curve toward the levels customer products need. The stage also produces the parametric data that device models depend on and starts reliability learning, so the qualification plan is built on early evidence rather than assumption.
In scope: test chip runs and measurement, parametric test data, defect inspection and review, failure analysis, the defect Pareto, the defect density trend, the yield model, the lithography hotspot list, the integration issue log, the reliability test plan and early reliability results. Out of scope: formal technology qualification, which is Process Reliability Qualification.
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