1. Purpose and scope
Modules that each meet their own targets do not yet make a working process. Every step changes the wafer that the next step receives: thermal steps move dopants placed earlier, etches and cleans attack films they were not developed on, planarisation depends on the pattern density left by lithography, and stress from one film shifts the devices beneath it. Process integration finds and resolves these interactions, first in short loops and then in full-flow lots, and tunes the flow until the devices sit near their targets with understood variation.
The end point is the process baseline, a frozen description of the integrated flow. The freeze matters because three expensive streams of work depend on it: the design kit's device models are fitted to its silicon, test chips and their yield learning run on it, and reliability qualification later tests it. A baseline that keeps moving makes all three unreliable. From the freeze onward, changes go through process change control.
In scope: the integrated process flow, short-loop and full-flow learning, device tuning and characterisation, released module specifications, final OPC models, test vehicle designs, the test vehicle mask set, the initial inline control plan and the process baseline. Out of scope: building design-start kit content and running test vehicles at scale for yield learning, which follow in PDK & Design Enablement Development and Test Chips & Yield Learning.
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