1. Purpose and scope
A photonic layout is made largely of curves. Waveguides bend with controlled radius, tapers change width smoothly and devices such as rings are circles, so the layout is drawn from parametric cells and scripted routing rather than by placing rectangles. Standard rule checks, written for grids of straight edges, can report many false errors on such shapes or miss real ones, so the verification flow must use decks built for curved geometry.
Layout also fixes where light leaves the chip and where the test probes reach it. Fibre couplers must sit where the package can align fibres to them, and test ports must be reachable at wafer test. The stage ends at layout sign-off, when design rule and connectivity checks are clean or waived with the foundry, post-layout simulation still meets the targets, and the package and electronic die interfaces match.
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