1. Purpose and scope
The decks are the rules in executable form. At sign-off, every chip on the node is accepted or rejected by them, so a check that misses a violation lets a defect reach the mask, and a check that flags clean shapes wastes designer time and erodes trust in the kit. The purpose of this stage is to code every rule in the manual as checks for each supported physical verification tool category, and to prove every check on layouts written to pass and to fail it.
Five kinds of deck are built. The design rule check deck codes width, space, enclosure, density and special device rules. The layout versus schematic deck recognises every device, its terminals and its parameters, and compares the layout's connectivity with the schematic. The antenna deck checks charge collection ratios during processing. Density checks confirm each layer stays within its windows. Electrical rule checks cover well and substrate connections and similar conditions. Deck QA then runs the full test case library in each tool category and compares the results.
In scope: the physical verification decks, the deck QA report and the deck ports for supported tool categories. Out of scope: DFM and lithography hotspot checks and fill decks, which belong to DFM Rules & Fill, and extraction decks, which belong to Parasitic Extraction & Technology Files, although both build on the layer derivations coded here.
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