1. Purpose and scope
On an advanced node, wires often decide timing, power and noise as much as transistors do. Every post-layout simulation, every timing sign-off and every power grid analysis on the node uses the parasitics produced by the kit's extraction decks. The purpose of this stage is to describe the interconnect stack faithfully, build extraction decks for each supported tool category and mode, and show by correlation with silicon and field solver references that extracted values meet the accuracy targets set in the plan.
The stage also writes the electromigration and current density rules that reliability analysis tools check, drafted from reliability data on the interconnect. They decide how wide power grids and high-current signal wires must be.
In scope: the interconnect technology file for each metal stack option, reference capacitance tables from field solvers, extraction decks, the extraction correlation report and the electromigration and current density rules. Out of scope: device models, which belong to Device Modelling, and the layout technology file used by layout and routing tools, which belongs to Layout Technology, PCells & Symbols.
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