1. Purpose and scope
The interface ASIC turns a tiny change in capacitance, charge, resistance or frequency into a calibrated digital output. It must add less noise than the transducer, cope with large parasitic capacitance and offsets, drive resonant structures where needed, survive overload and shock, and do all this at very low power. Its trim circuits must cover the spread of a mechanical device that varies more than most electronic components.
Because the transducer is part of the signal path, the ASIC cannot be verified alone. Co-simulation with a behavioural model of the transducer checks start-up, closed loop stability, nonlinearity, electrostatic pull-in margins, self-test and the effect of transducer spread on the readout. The trim and register map is fixed here, and with it what calibration and firmware can later correct. The sensor interface, such as I2C, MIPI I3C or SPI, is verified against its standard with verification models, and a conformance test plan is written for silicon.
In scope: the interface ASIC specification, the calibration and trim architecture, the trim and register map, circuit design and layout, co-simulation verification, the firmware architecture, the interface conformance test plan and the tape-out database. Out of scope: MEMS layout, which is released in MEMS Process Development, and silicon evaluation, which happens in Prototype Build & Model Correlation.
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