1. Purpose and scope
A memory array is millions of identical cells, which makes it a very good instrument for finding process problems. Test vehicles with full or partial arrays, cell monitors and defect structures are run on the baseline, tested for retention, disturb and endurance, and their failures are mapped bit by bit. The pattern of failing bits, whether single bits, rows, columns, blocks or clusters, points to the process step that causes them.
This stage drives defect density and cell spread down until the array yields on a trend that supports a product die, with the main fail mechanisms understood and repair able to cover what remains. It also gives reliability its first look at intrinsic cell behaviour. The output is not only yield: it is a yield model the product die's redundancy and error correction are sized on.
In scope: test vehicle layout and patterns, testing, fail bit map classification, defect and inline correlation, the defect Pareto, the yield model and the intrinsic reliability assessment. Out of scope: wafer test and repair of the product die, which belongs to First Silicon & Characterisation.
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