1. Purpose and scope
A memory maker usually develops its process together with its product. The process is tuned to one cell and one array, and its hardest steps are the ones that form the array: printing very dense repeating lines and holes, etching deep narrow structures, forming capacitors or stacks of many layers, and keeping all of this uniform across the wafer. This stage develops those modules, joins them into one integrated flow with the peripheral transistors and interconnect, and freezes a memory process baseline that the product die can be designed on.
The baseline is not only a recipe. It comes with process design rules and device models good enough for product design, and an internal design kit that packages them. The circuit designers in the next stages rely on those rules and models, so their maturity and their version lock matter as much as the wafers. The process node lifecycle covers process development in general; this guide focuses on what is specific to memory.
In scope: module development, integration lots, device characterisation, model extraction, rules and decks, and the baseline freeze. Out of scope: array yield learning on test vehicles, which belongs to Test Chips & Array Yield Learning, and the shrinks of a process already in volume, which belong to Cost-Down Shrinks & Derivatives.
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