1. Purpose and scope
A memory die is unlike most chips. Most of its area is a full custom array and the analog periphery that reads and writes it, designed and verified at transistor level; only a small part is synthesised logic. The design must meet the timing and electrical behaviour of a published standard exactly, because the part will be used with controllers the memory maker did not design, and it must carry enough redundancy, error correction and test access to make the yield model work.
This stage takes the array and periphery architecture to a verified die with its layout complete and extracted. It opens at Stack design freeze, when for stacked products the stack architecture, through-silicon via plan, bump map and base die interface are frozen, and closes at Design verification sign-off, when the circuits, the behaviour and conformance to the standard are verified on the extracted layout. Layout & Tape-out then finishes the full chip and releases it to mask making.
In scope: circuit design and simulation across corners, interface and I/O design, signal and power integrity, behavioural model and conformance verification, custom layout of the array tiles and periphery for extraction, and stack co-design. Out of scope: full chip physical verification, reliability checks and the tape-out checklist, which are done in Layout & Tape-out, and test program development for the die, which starts here but is completed in First Silicon & Characterisation.
12 more sections for registered members.