1. Purpose of the gate
The shrink or derivative die is designed and verified on the improved process and its tape-out database is released to mask making, which starts the shrink's own silicon, characterisation and requalification.
A shrink is a second design cycle on a product that is already in volume. The approval at the start of the stage decided that the cost per bit case and the requalification scope justify the work; this gate decides that the design itself is ready to commit to masks. Masks for dense memory layers are expensive and slow to replace, so the review is as strict as the original tape-out, even where most of the array and periphery are carried over.
The review looks hardest at what changed. The shrink process baseline brings new design rules, new device models and often a new cell, so circuits that were safe on the original node have to be shown safe again: sense margins, retention, disturb behaviour, timing across corners and the redundancy and repair scheme that covers the new defect pattern. Interface timing and signal integrity are rechecked against the standard the part conforms to, because customers expect the shrink to behave as the original did.
The gate is the shrink cycle's own engineering milestone on the maturity ladder. The ladder restarts at the shrink approval, so the shrink's design maturity is judged on its own evidence rather than inherited from the original die.
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