1. Purpose and scope
This stage produces the analytical and test evidence that the design meets its integrity and security targets. It answers three questions an assessor will ask. Do the random hardware failure measures meet the target, on analysis with credible failure rates and diagnostic coverage? Are dependent and common cause failures controlled? And does each requirement, including each security requirement, have a verification result?
The final FMEDA replaces estimates with the frozen design, the chosen failure rate source and diagnostic coverage that is supported by evidence. Fault insertion testing provides that evidence: faults are forced on real hardware, by pin forcing, supply and clock manipulation, or in simulation and emulation, and each diagnostic is shown to detect them and reach the safe state in time. A coverage claim without fault insertion behind it is one of the most frequent assessment findings.
Security verification follows the verification practices of IEC 62443-4-1: testing each security requirement, scanning for known vulnerabilities, fuzzing every interface and parser, and penetration testing by people independent of the developers. The stage ends when the evidence is complete and no high-severity finding is left open.
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