1. Purpose and scope
A hard macro cannot be fixed after tape-out without a new layout, a new sign-off and a new test chip, so the bugs it carries into layout are expensive. This stage verifies the design before layout against the verification plan: every function in simulation, every circuit at every agreed corner, the sensitive analog circuits across process variation and mismatch, and the analog and digital parts together in mixed-signal simulation.
The stage has a second purpose that is specific to hard IP. SoC teams that will integrate the macro must start their floorplans well before the macro's layout is done. They need its footprint, its pins and blockages, and a preliminary timing and power model. The early views release gives them these, clearly marked preliminary and with their basis stated, so they can reserve space and route around the macro without waiting for sign-off.
The early views must be honest about their limits. A preliminary timing model built from schematic simulation will move once the layout parasitics are known, and the release notes say how far it may move. An early abstract whose footprint later grows is one of the most disruptive changes an integrator can receive.
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