1. Purpose and scope
A silicon-proven release is a claim integrators rely on when they commit their own chips to production. This stage makes sure the claim is backed by evidence and that the package an integrator receives is complete, consistent and usable. It audits every deliverable against the quality checklist: the GDS, the abstract, the timing and power views updated with silicon correlation, the circuit and behavioural models, the test patterns, the datasheet, the integration guide, the silicon report and the errata.
Consistency matters as much as completeness. The views must describe the same macro as the GDS, the integration guide must match the pins and supplies in the views, and the datasheet must state what silicon showed rather than what simulation predicted. Each item carries the version of the macro it belongs to, so an integrator can tell exactly what they received.
Two gates close the stage. The Hard IP quality sign-off confirms the deliverable set, with its silicon and reliability evidence, has passed the checklist. The silicon-proven release then publishes the versioned package to SoC teams and licensees with its silicon report, errata and a route for support.
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