1. Purpose and scope
Layout is where a hard macro becomes the thing that is delivered. The integrator will place the GDS as a whole, so everything inside it, from matched device pairs to the last power strap, is the macro team's responsibility and cannot be changed by the SoC. The stage builds that layout on the target process and metal stack: custom layout for analog and sensitive circuits, placement and routing for digital parts, and the pins, power grid, guard rings and isolation that tie them together.
The layout must respect the contract with integrators. The footprint and pins published in the early views are kept, or any change is agreed and announced. The metal layers the macro may use are kept, and those reserved for the SoC above the macro are left free or blocked as agreed. Pins sit on the sides and layers integrators expect, with the spacing and access their routers need.
Two other pieces of work finish in this stage. The reliability design review checks the layout for protection against electrostatic discharge, latch-up and electromigration before sign-off, when fixes are still cheap. The test chip specification is finalised, so the test chip can be built around the frozen layout. The design and layout freeze closes the stage; after it, only fixes found by sign-off and verification are accepted.
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