1. Purpose of the gate
A preliminary abstract, pin list and timing model go to SoC teams so they can floorplan around the macro, with their limits stated.
Integrators cannot wait for sign-off to start their floorplans. The early views give them what they need to reserve space and plan routing: the footprint, pins and blockages, and a preliminary timing and power model. This gate decides whether those views are good enough to release and whether their limits are stated honestly.
The review checks that pre-layout verification of the main functions has passed, that the floorplan and pin placement are final, and that the abstract matches them. It checks the basis of the preliminary timing and power model and the movement expected when layout parasitics are known.
It also starts the planning that will be needed later: the validation plan, the reliability requirements and the deliverables checklist all begin here from the specification.
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