Chip, package and board co-design

The die, its package and the boards it sits on are one electrical, thermal and mechanical system, so they are designed together rather than one after the other. Across the SoC programme the co-design work runs as a series of iterations, one for each maturity level on the chart's scale, and each iteration closes at a gate: a concept pass at specification freeze, first bump and ball maps at RTL freeze, full substrate routing and the first combined analysis at verification sign-off, a complete and co-verified package design at DFT insertion sign-off, and a frozen die file and package design at physical sign-off. Each iteration takes its inputs from the die, package and board teams, produces outputs at a higher maturity, and hands those outputs to the next iteration as inputs. After tape-out the frozen design is built, assembled and measured, and the results are correlated with the models. The iterations line up with the physical design place-and-route (APR) flow. The concept and first-map iterations run alongside floorplanning and power planning: the floorplan places the I/O cells, hard macros and bump regions, and the bump map in turn fixes where power enters the die grid. The feature-complete iteration uses the trial place-and-route runs: the trial layout gives real bump and pad positions and a chip power model from on-die IR drop analysis, and the package team returns extracted package models so on-die power integrity is analysed with the package attached rather than an ideal supply. The complete iteration runs during timing and physical closure on the near-final layout, and the freeze closes with chip finishing, when the final layout database is compared against the frozen die file. Any bump or ball change found in a later iteration loops back to the floorplan and power grid of the place-and-route flow, which is why bump changes get harder and more formal at each gate. The iterations also line up with board design for bring-up. The board team agrees stack-up and escape assumptions in the concept pass, receives the feature-complete ball map for schematic capture and placement, receives package models, IBIS models and the package outline drawing for layout at the complete iteration, and releases the validation and reference boards for manufacture once the ball map is frozen, so that boards, sockets and test hardware are ready when the first packaged parts arrive. Findings from bring-up feed reference board updates and, where the package itself must change, a formal change for the next substrate build or silicon revision.