1. Purpose of the gate
Coverage goals are met for the fabric, the configuration logic, the security features and the hard IP connections, and every open bug is fixed or waived with a recorded reason.
Verification sign-off is the last point at which a functional bug is cheap. The review checks that the verification plan's coverage goals are met for every area of the device and that each gap is either closed or waived with a reason the reviewers accept.
For an FPGA the plan has areas few chips have: the configuration controller and its interfaces, the frame addressing of the configuration memory, partial reconfiguration, readback and upset detection, and the security features, including what the device does when authentication fails, when a key is missing or when tampering is detected. Failure and tamper responses are verified on purpose, not assumed from the normal path.
Configured design simulation, where the device model runs bitstreams from the vendor's own software, continues to the pre-silicon software readiness gate, but the review checks that it has started and that its failures are triaged with the software team.
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