1. Purpose of the gate
Before the fabric architecture is frozen and development is committed, the team shows that the process, the configuration memory technology, the critical hard IP and the package can meet the family's targets, or records each gap and how it will close.
The exploration results compare candidate fabrics using estimated building block delays and areas in the target process. Those estimates rest on the process, on the device used for the configuration memory, on hard IP that may not yet exist in that process, and on a package large enough for the biggest member. Before the fabric is frozen and development committed, this technical readiness review asks whether those technologies can deliver what the exploration took for granted.
Four criteria apply. The process and configuration memory technology must be shown able to meet density, speed, power and reliability targets with data at an agreed maturity. The silicon status of every critical hard IP block must be known, with a plan for each gap. The package and input and output technology must be shown feasible for the largest member. Open technology risks must be listed and tracked.
Configuration memory deserves particular attention. Its cell is repeated more than any other circuit in the device, and its upset behaviour, leakage or retention, depending on the technology, sets what the family can claim for reliability. A configuration memory that is marginal in the process is a family-wide risk, not a block-level one.
Finding a gap here costs a re-plan of the fabric or the member order. Finding it after the fabric freeze costs reworked tiles and software; finding it at bring-up can cost a revision of the first member.
10 more sections for registered members.