1. Purpose of the gate
The fabric and the hard IP have been measured across voltage, temperature and process corners, and the measured delays have been compared with the pre-silicon timing models.
Characterisation is what turns simulated timing into measured timing. This gate checks that every resource the timing models describe, logic, routing segments, block memories, arithmetic blocks, clocks and input and output, has been measured across the agreed corners, and that the measurements are traceable to timing model elements.
It also checks that the differences from the advance models are explained. A difference may come from a tile view, from extraction, from the model structure or from the silicon, and each needs a cause before production timing data is built.
Material matters. Parts from across the process window, where the foundry can provide them, show how delays spread. Timing data built only on typical parts does not hold for the slow end of production.
The method matters as well. Most fabric delays cannot be measured directly on a single path, so characterisation configurations such as ring oscillators and chains of routing segments are used, and delays are derived from them. The review checks that each derivation is sound, that the structures include the loading a real design sees, and that the same structures can later be used in the binning tests so production test and characterisation stay correlated.
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